DDR I/II/III Memory Controller Core
ASIC Architect’s DDR I/II/III Controller Cores are an integral part of the product portfolio aimed at providing a complete end-to-end solution in the High Speed Interface Controller domain. The DDR controller cores have been architected, designed and verified by ASIC/SoC industry veterans. The add-on solution cores that come with the DDR Controller accelerate the chip-level integration by connecting multiple clients to the DDR Controller. The DDR controller core handles all complex functional aspects of controlling a DDR SDRAM for initializing the memory devices, translating the read and write requests from the application interface into the standard SDRAM command signals, performing ECC for the memory banks. It also provides a powerful application interface to handle multiple application clients with an agent ID based mechanism to route read-completion data to application clients.
Brief Product Overview
ASIC Deliverables
- Synthesizable Verilog RTL
- Testbench and Models for Simulation
- Complete User Integration Manual
- Sample Synthesis and Static Timing Analysis Scripts
- Support from Core Integration through Silicon Bring-Up