ASIC Architect

Santa Clara, CA, July 28, 2005 -- ASIC Architect, Inc., a leading provider of Cores and Solutions for PCI Express, today announced that PCI-SIG has included ASIC Architect's Endpoint Controller for PCI Express to its Integrators List. ASIC Architect has passed PCI-SIG-defined protocol, configuration, electrical testing, and successfully completed PCI-SIG's compliance checklist. The product has passed interoperability testing with Rootcomplex/Switch/Bridge vendors for PCI Express at the Compliance Workshop.

“We are proud to work with ASIC Architect to provide our board level expertise. The DINI Group and ASIC Architect focus on their core strengths, and provide one-stop complete solution to our Customers for PCI Express,” says Mike Dini, President of The DINI Group.”PCI Express is a complex technology, and partnering with ASIC Architect benefits our customers.”

“Our company's focus is PCI Express, and we are passionate about this technology. We are committed to bringing the best products and solutions to our customers in the domain of PCI Express. We passed PCI-SIG's Compliance and Interoperability Testing for PCI Express in our first attempt. This validates our stringent IP Core design, verification and silicon validation methodology,” said Kishore Mishra, President and CEO of ASIC Architect. “We provide full-range of Cores for PCI Express – Endpoint, Rootcomplex, Dual Mode – Root Port and Endpoint, Switch Port Cores and other solution logic that helps the customers to quickly integrate our core into their logic. We standby our customers from core integration through silicon bring-up.”

“We are happy to see ASIC Architect become a part of the growing PCI Express Integrators List,” said Tony Pierce, PCI-SIG Chairman. “PCI-SIG member companies, like ASIC Architect, play a major role in accelerating the adoption of PCI Express technology in the industry.”

About ASIC Architect Products:
ASIC Architect offers a wide range of Cores for PCI Express – Endpoint, Dual Mode – Root and Endpoint, Root Complex, Switch Port and related Solutions for ASIC and FPGA.

Key Features:

• PCI Express Specification 1.0a or 1.1 Compliant
• Low Gate and Memory Count
• Low Transmit and Receive Latency
• Supports x16, x8, x4, x2, x1 Lanes
• Choice of 32/64/128 bit Datapath on Application Interface
• Choice of Single or Dual PIPE Mode on Phy Interface
• Technology Independent Design for ASIC, FPGA
• Excellent Support from Core Integration through Silicon Bring-up